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9 comments :

HariPranav Dharmalingam said...

greeting!
I am an electronics engineering student and i am using Quartus II as a software for HDL. As i try out programs in structural modelling, I get an error saying that the nodes i use to call the components are undefined.
"Node instance 'H1' instantiates undefined entity HALFADDER"
I would greatly appreciate it if you would he;p me with this.
thank you.

Kriti said...

Sir, I need the behavioral, structural and data flow codes for RAM and ROM for my project urgently. Please help me with the same.

Anonymous said...

Hi, I am pretty much struggling with my project. This is what I was assigned.
You need to create an 8-bit parallel in/parallel out shift register. You need to create a JK-FF and a T-FF. Every bit in the shift register should change the FF type. Bit 0 JK, Bit1 T, Bit2 JK, Bit3 T, etc.
The shift register should be made with the flip flops as components.

CAN YOU HELP ME OUT CODING THIS.

Thank you.

Anonymous said...

Hi....can you provide vhdl code to find an antilogarithm of a fixed point number of 16 bit precision..
Thank you

Sonali Gupta said...

Hi sir,i have to make the code for Spi to Arinc 429 interface.Can u please provide the code for the same(the data which is in SPI format hve to be coverted in ARINC 429 word format.)
Sir please help me out.i need it urgently.
Thank you.

Anonymous said...

Sir, i am using this
bor<='0' when (s="000" or "100" or "101" or "110") else
'1' when (s="001" or "010" or "011" or "111") else
'Z';
for full subtractor using when else.. but i am getting error with 'or' , when i use each case singly, it works fine.. Shouldn't we do like this ??

Avinash said...

Hello Sir,

I need to optimize my VHDL code which is now consuming 78% of Logic elements in the design. We have a lot of sync circuits and clocks in the code.

Please let the possible solutions to optimize so that the logic elements utilization can be reduced below 60%.

Anonymous said...

sir plz update programs
1. procedure for sorting two inputs of byte size.
2.4 bit subtracter using concatenation

Anonymous said...

I am need to know how to implement time constraint analysis of MUX in VHDL.help..

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