Tuesday, 30 July 2013

The Three Basic Element inside a Computer Chip






Three Basic Element inside a Computer Chip -



Three Basic Elements inside IC (Learn VHDL with Naresh Singh Dobal series).





       There are three basic elements in a computer chip, First one is called a transistor and this is the switch just like a light switch, that turn on or off, and flows and block the electricity, this is the three terminal device. 

     Next one is resistor, and resistor slows down the electricity, when electricity passes threw the resistor then it resist the flow of electricity, it’s symbol is like a zigzag line, and this is a two terminal device, and this is very important in electronics, Resistors comes in different values and different sizes. If you see them in real then you can see some band of colors these band actually tells the value of resistance, don’t worry about that I will tell you that how you can identify the value of resistors using color bands.

      The third most important part of an integrated circuit or computer chip is capacitor, and a capacitor stores the electricity, These capacitors makes up of different materials and different sizes, this is basically a two terminal component.
So now if you connect these all components a resistor, transistor and capacitors with the help of wires then you have a some type of electronic circuit. 

Let's start with making a Semiconductor Chip






Lets start with making a Semiconductor Chip -


Let's start with making a semiconductor chip (Learn VHDL with Naresh Singh Dobal series).




        So now let’s talk about that how do you make these amazing computer chips. Before that we should understand what are Integrated circuits, just think like that, a chip is a switch like a light switch, when you turn on the switch then the electricity goes threw it, and light will turn on, and when switch is off, then it’s blocks the current and light will off. So in the case of semiconductor it’s partially conduct the electricity threw it. So when it is ON electricity goes threw it and light will on, and when it is off then its blocks the current and light will off. So now you know every thing about the chip, that they are simply the switch, Cool na… so now you may surprise that ohhh the computer chips are only just like switch! But this is little bit complicated than that, The important thing about these switch are they are made up of sand, and in our semiconductor industry it’s means to silicon. Silicon is the most abundant element on earth. This is very good material to integrate these switches. I recently learn that most of the sand comes from Australia. Because there sand is more pure. 
       So now lets talking about the switches, so there are two switches, and you can see at the left when switch is off, then there is no flow of electrons and no flow of current, and in the right image when switch is on, the electrons flows to the other terminal and current flows, so turn these switches on and off like turn it on, turn it off, turn it on and so on, the electricity flows and blocks, according to switch through out the computer chips. Very simple it is.

Let's know about our Semiconductor Industry






Lets know about our Semiconductor Industry -



Let's know about our semiconductor industry (Learn VHDL with Naresh Singh Dobal series)


      So friends, why we are here, I mean to this semiconductor industry. Obviously to make a lot of money, so lets talk about the industry in general, that how important we are, what we do, and how we can make money from this industry, First I would like to tell you some fact about this industry that how big actually this semiconductor industry is, means how much cost of computer chips resell each year, this is approximately 300 billion dollars, this records is according to the year 2010 but today is 2013, so that numbers must be higher, that is our gole, if we talking about the EDA industry then that is about 5.3 billion dollars, The interesting thing is that none of the computer chip and electronic chip will be exist without this EDA industry.


    Now the market drivers, that means to the selling of electronic chip to consumer, The most important thing about the market driver is time to market, that means you have to move the products to the market on time, this is because we generally knows this term that there are some occasions when the demands is high for example many of us plans to purchase a computer system or any other electronic gadgets on Diwali or other festivals, so at that peak time if company is not delivers the products, that reduces the profit, now another critical aspect which effect the vlsi industry is global competition, the chip industry or semiconductor industry was mainly based on US market, few years back Japanese said that they produce the electronic chip cheaper, faster and better quality, and they really affects the US semiconductor market, The US developer says ohhh we don't want to loose the semiconductor market, and takes some major steps. But interesting thing is that, now the semiconductor or chip industry is approximately all over the world. primarily in twain. This was quite interesting. And other aspects are the technology which is use to make chips smaller, faster denser, and lower cost and better quality. Because if you remember the early cell phones they are bigger at 10000Rs, but today you will get these cell phones in 500Rs only, so the cost is lower and lower, and size of systems is also reduces, and it's now smaller, smaller and smaller, so I must say that this technology is very interesting, dynamic, and challenging.

Computer Chips are EveryWhere (Application of Electronics CHIPS).






Electronics Chips are Every Where -


Computer Chips are every where (Applications of IC)  (Learn VHDL with Naresh Singh Dobal)




        Yes, This is right Computer chips are absolutely every where and in every field, even that places you dont't imagine, so they are in your computers and cellular phones, in your tablets, they are in your gaming systems  like xbox, play stations, they are in i-pods, DVD Players, TV's, watches, They are in automobile like cars, bikes, etc pacemakers, satellites, electronic greeting cards like when you open that some type of sound play from it, So you can say that electronics chips are every where - In communication, medical, Industrial automation, PLC devices, controlling instruments, Electronic gadgets, daily use appliances, in traffic lights etc.

Very Important ACRONYMS & TERMS of Semicondutor Industry.






Important   ACRONYMS -




Important Acronyms & Terms of Semiconductor Industry (Learn VHDL with Naresh Singh Dobal).




            


           So Friends my first question to you is, that what we are, in this electronic semiconductor industry, We are EDA, i.e Electronic Design Automation, As the name indicates that we automating the design of electronics, That means we use computers to design all these complicated chips that may be used in Ipods, Laptops, Display systems, Sound systems, cell-phones, Tablets, Industry automation system, security system, medical etc.  

            The next important thing is CAD that is Computer Aided Design, in the past few deades we are using CAD Tools in every field like mechanical design, civil design, automobile design, IC design, system design etc.

          This is the very important thing in EDA industry that is HDL called Hardware Description Language. This is actually a computer Language, This is very important in VLSI Industry, using HDL we tell the computer to help in design of any integrated circuit, HDL's are working on the same manner that other programming language works that you give some commands to the computer, like computer do this, computer do that .. in this manner. There are many HDL's in market, Here I am telling you about the most popular HDL i.e   VHDL.

         VHDL, stands for  Very High Speed Integrated Circuit Hardware Description Language. Another popular language is Verilog & System Verilog.  So as all other competitive languages there is a language war, that some says VHDL is better, some says no Verilog is good, and some says System Verilog is good. But this is not in that manner, all the language do the same thing but in different manner, It's just like same, some says English is good, some says hindi is good. So people can choose that which they want to use. This may be choose by designer, or by a company or Country wise as well.

          The next important term is RTL,   RTL stands for Register Transfer Level, This is very common term used in EDA industry, This is basically a collection of subsets or collection or commands or the blocks of electronic components having some type of combination or sequential circuit or the basic logical gates.

        PLD's are Programmable Logical Devices, as name suggests, that the devices which can Program a Logic inside it are named as PLD's. There are many type of PLD's in market like PLA (Programmable Logic Array), PAL (Programmable Array Logic),  PROM (Programmable ROM),  SPLD (Simple PLD),  CPLD (Complex PLD), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit).

         ASIC stands for Application Specific Integrated Circuit. First we take a example of general purpose chips like a intel processor, I put that chip in a microwave oven and I say cook my food, and then i places that chip into a traffic light and I say "change the signals according to traffic density", then I put that chip into a security system and say when some one enter in my room then play some sound, Or i place it into a mobile and say ring when someone is calling me, So this a a example of general purpose chips, but if i want a chip that only performs a one very tiny tiny specific function that no other chip can do.So that chip is very much specific to my own application, so lets say I want to make a chip which only tell me when some one walks in my home, that can be specific function, so ASIC are the specific type of chips.

            FPGA : FPGA stands for Field Programmable Gate Array. This is a special type of chip, which can be use for general application, and the more things about FPGA's We will discuss later. When we work on that chips.

           Platform : Platform is basically a foundation where some thing can be stand, but if we talk about VLSI industry then platform means the collection of EDA tools.

           IP : This is a very important term in EDA industry, that may confuse to you with the IP i.e. Internet Protocol, but we nothing to do from that IP in our industry. In our industry IP stands for intellectual property, and there is mainly two expect of intellectual property. So what is Intellectual Property, these are our ideas or inventions or creations which are generated in our head and the reason of intellectual property is so important because if some one steal your ideas and do's that same things, and often gets money it's not related to there business but it's hurts, and This is really a bad thing. So our industry plans of IP. Using these IP we protect the intellectual properties with legal agreements, so intellectual properties is very very important, the second things about the intellectual property is also mean design, chip design and if I come with this brilliant idea of design but I want to protect that and I also want to reuse that so I can build bigger things at top level, so  IP's are the building blocks in a comlex chip designs. And we can use that in the top level designs. Fact is There are thousands of employees works in a industry, but the major thing is ideas, mind, creations, logical thinking, designing abilities.

          Semiconductor : Semiconductor, I am explaining this term in very simple way, semi means partial, conductor means conducting of electricity so what is semiconductor means that some other time this conduct the current threw it or some other times this blocks the electricity.

          IC : IC are integrated circuits or integrated chips.
 




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Monday, 29 July 2013

Electronics - Trends Setting Points







Electronics : Trend Setting Points   (Learn VHDL with Naresh Singh Dobal Series)



          First  I  would like to tell you few interesting things about the trends setting point of this semiconductor industry and electronics. According to a record that is found that the word  "electronics" has first comes in 1894,   Mainly in 1946 or before our early electronics computers use glass valves they called vacuumed tubes. What very interesting that the first electronics computer called INAC that have 18000 valves, that have a weight of 30 tons and takes the power required for the 10 homes. So amazing today's now we dont' take a computer having the weight of 30 tons, now you have the small computers in 1-2 kg only or may be less. Basically the early glass valves glows and produced heat to perform operations. So we have to use very effective cooling environment and ventilation system and the important thing is that when the system fails the debugging of these valves were very difficult.

            In 1947 a first transistor was developed in bell labs, don't worry I will show you a transistor after some time, Early Transistors are near about 40 to 45 dollars, and now the transistors are only 15 cents or less.

           In 1954 a fully Transistorised computer was developed and it was invented by IBM, and this take 2000 separate transistors.


           In 1958 the first integrated circuit normally called IC was invented at Texas Instruments.

           In 1971 the first microprocessor was invented by INTEL, this first microprocessor having 2300 integrated transistors, INTEL - you know about intel that is in intel inside logo, most of the computers and laptops in today life are working on INTEL processors.

           In 1975, this is the most important concept which was developed, and the concept was that the chip complexity i.e How much components or transistors implemented on a single chip, it was predicted that the chip complexity will be double in every 1 and half years,  This concept is called Moore's Law in our industry,  But His original prediction was in 1965, and He said that the number of transistors will be twice in each and every year. But in 1975 after 10 years of that prediction what they found that the chip complexity will be double in every 2 years. So our industry decided according to moore's law and result of last decade that the chip complexity will be twice in every one and half year (18 months), and till this day that is 2013 the moore's law continuously running in the industry.

           In the last point of that history in year 2011 the INTEL again introduced 10 core xion weasteren processor, This particular microprocessor has 2 billion 600 million transistors in a size of your finger point.






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World of Integrated Chips AND Electronic Design.







World of Integrated Chips and Electronic Design with Naresh Singh Dobal.



      Welcome you ALL in the ERA of this Interactive session  named  "World of Integrated Chips and Electronic Design,  I  am   "Naresh Singh Dobal",   and I am going to give you some amazing information's about our Semiconductor Industry.

        This small series will give you an idea about the VLSI chips, like how the computer chips are manufacture and how they are designed, This small Tutorial will develop a basic understanding of Semiconductor Industry, Don't Worry about this semiconductor term, I will explain that in my next session,   and more about the EDA,    EDA  is   Electronic Design Automation.

        I will tell you that how EDA are important to our semiconductor industry, because we actually in EDA a small industry, but we belongs to this great thing called Semiconductor Industry.

Also we will follow the very simplified steps to process the manufacturing of computer chips and their designing.


I really would love for everybody to ask questions to make this tutorial, a interactive series...




                                                                                                                          Next Page   



Design of 8 : 3 Priority Encoder using std_match function and if - else statements (VHDL Code).






Design of 8 : 3 Priority Encoder using    std_match   function and if - else statements -


Output Waveform : 8 to 3 Priority Encoder


Output Waveform : 8 to 3 Priority Encoder




VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : priority_encoder_8_3
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- Verilog HDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of Priority Encoder using if else statements.vhd

   

library IEEE;
use IEEE.STD_LOGIC_1164.all;     
use ieee.numeric_std.all;

entity priority_encoder_8_3 is
     port(
         din : in STD_LOGIC_VECTOR(7 downto 0);
         dout : out STD_LOGIC_VECTOR(2 downto 0)
         );
end priority_encoder_8_3;


architecture priority_enc_arc of priority_encoder_8_3 is
begin

    pri_enc : process (din) is
    begin
        if (std_match(din,"1-------")) then
            dout <= "000";
        elsif (std_match(din,"01------")) then
            dout <= "001";
        elsif (std_match(din,"001-----")) then
            dout <= "010";
        elsif (std_match(din,"0001----")) then
            dout <= "011";
        elsif (std_match(din,"00001---")) then
            dout <= "100";
        elsif (std_match(din,"000001--")) then
            dout <= "101";
        elsif (std_match(din,"0000001-")) then
            dout <= "110";
        elsif (std_match(din,"00000001")) then
            dout <= "111";
        end if;
    end process pri_enc;
   

end priority_enc_arc;

Design of 8 : 3 Priority Encoder using if - else statements - Method 1 (VHDL Code).





Design of 8 : 3 Priority Encoder using IF-ELSE Statements -


Output Waveform : 8 : 3 Priority Encoder



Output Waveform : 8 to 3 Priority Encoder



VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : priority_encoder_8_3
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- Verilog HDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of Priority Encoder using if else statements.vhd

   

library IEEE;
use IEEE.STD_LOGIC_1164.all;     
use ieee.numeric_std.all;

entity priority_encoder_8_3 is
     port(
         din : in STD_LOGIC_VECTOR(7 downto 0);
         dout : out STD_LOGIC_VECTOR(2 downto 0)
         );
end priority_encoder_8_3;


architecture priority_enc_arc of priority_encoder_8_3 is
begin

    pri_enc : process (din) is
    begin
        if (din(7)='1') then
            dout <= "000";
        elsif (din(6)='1') then
            dout <= "001";
        elsif (din(5)='1') then
            dout <= "010";
        elsif (din(4)='1') then
            dout <= "011";
        elsif (din(3)='1') then
            dout <= "100";
        elsif (din(2)='1') then
            dout <= "101";
        elsif (din(1)='1') then
            dout <= "110";
        elsif (din(0)='1') then
            dout <= "111";
        end if;
    end process pri_enc;
   

end priority_enc_arc;

Design of 8 : 3 Priority Encoder using std_match function (when - else) VHDL Code.







Design of 8 : 3 Priority Encoder using    std_match   function  & When - Else

Output Waveform : 8 : 3 Priority Encoder



Output Waveform : 8 : 3 Priority Encoder


 VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : priority_encoder_8_3
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- Verilog HDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of 8 to 3 Priority Encoder using when else.vhd

   

library IEEE;
use IEEE.STD_LOGIC_1164.all;  
use ieee.numeric_std.all;

entity priority_encoder_8_3 is
     port(
         din : in STD_LOGIC_VECTOR(7 downto 0);
         dout : out STD_LOGIC_VECTOR(2 downto 0)
         );
end priority_encoder_8_3;


architecture priority_enc_arc of priority_encoder_8_3 is
begin
   
dout <= "000" when std_match (din,"1-------") else
        "001" when std_match (din,"01------") else
        "010" when std_match (din,"001-----") else
        "011" when std_match (din,"0001----") else
        "100" when std_match (din,"00001---") else
        "101" when std_match (din,"000001--") else
        "110" when std_match (din,"0000001-") else
        "111" when std_match (din,"00000001");
   

end priority_enc_arc;
 

Design of 8 to 3 Priority Encoder using When Else statements -Method 1 (VHDL Code)






Design of 8 to 3 Priority Encoder using When-Else Statement - Method 1 



Output Waveform 1 :  8 to 3 Priority Encoder

Output Waveform :   8 to 3 Priority Encoder




VHDL Code-



-------------------------------------------------------------------------------
--
-- Title       : priority_encoder_8_3
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- Verilog HDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of 8 to 3 Priority Encoder using when else.vhd

   

library IEEE;
use IEEE.STD_LOGIC_1164.all;  
use ieee.numeric_std.all;

entity priority_encoder_8_3 is
     port(
         din : in STD_LOGIC_VECTOR(7 downto 0);
         dout : out STD_LOGIC_VECTOR(2 downto 0)
         );
end priority_encoder_8_3;


architecture priority_enc_arc of priority_encoder_8_3 is
begin
   
dout <= "000" when din(7)='1' else
        "001" when din(6)='1'else
        "010" when din(5)='1' else
        "011" when din(4)='1' else
        "100" when din(3)='1' else
        "101" when din(2)='1' else
        "110" when din(1)='1' else
        "111" when din(0)='1';
   

end priority_enc_arc;

Design of 8 nibble Queue using Behavior Modeling Style (VHDL Code).






Design of 8 nibble Queue using Behavior Modeling STyle -


Output Waveform :  8 nibble queue design



VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : queue_8nibble
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of 8 nibble queue using Behavior Modeling Style.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity queue_8nibble is
     port(
         clk : in STD_LOGIC;
         push : in STD_LOGIC;
         pull : in STD_LOGIC;
         din : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end queue_8nibble;


architecture queue_8nibble_arc of queue_8nibble is

type mem is array (0 to 7) of std_logic_vector (3 downto 0);

signal queue : mem := (others=>(others=>'0'));

begin

    queue_design : process (clk,push,pull,din) is   
    variable mem : std_logic_vector (3 downto 0) ;
    variable i : integer := 0;
    begin                   
        if (rising_edge (clk)) then
            if (push='1') then
                queue(i) <= din;  
                if (i<7) then
                    i := i + 1;       
                end if;
            elsif (pull='1') then   
                dout <= queue(0); 
                if (i>0) then
                    i := i - 1;
                end if;
                queue(0 to 6) <= queue(1 to 7);
            end if;
        end if;
    end process queue_design;
   

end queue_8nibble_arc;

Design of Parallel In - Serial OUT Shift Register using Behavior Modeling Style (VHDL Code).






Design of Parallel IN - Serial OUT Shift Register using Behavior Modeling Style -

Output Waveform : Parallel IN - Serial OUT Shift Register





VHDL Code-




-------------------------------------------------------------------------------
--
-- Title       : parallel_in_serial_out
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Parallel IN - Serial OUT Shift Register.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity parallel_in_serial_out is
     port(
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         load : in STD_LOGIC;
         din : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC
         );
end parallel_in_serial_out;


architecture piso_arc of parallel_in_serial_out is
begin

    piso : process (clk,reset,load,din) is
    variable temp : std_logic_vector (din'range);
    begin
        if (reset='1') then
            temp := (others=>'0');
        elsif (load='1') then
            temp := din ;
        elsif (rising_edge (clk)) then
            dout <= temp(3);
            temp := temp(2 downto 0) & '0';
        end if;
    end process piso;

end piso_arc;

Saturday, 27 July 2013

System Design using Loop Statements (Behavior Modeling Style)





Loops Statements (Behavior Modeling Statements) -



FOR Loop Syntax -


for    identifier    in    range    loop

      Sequential Statements ;

end loop;





Sample Programs for Loops Statements -


Design of 4 Bit Adder cum Subtractor using Loops (Behavior Modeling Style) (VHDL Code).






Design of 4 Bit Adder cum Subtractor using Loops (Behavior Modeling Style) -

Output Waveform :  4 Bit Adder cum Subtractor



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : adder_subtractor_4bit
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : 4 Bit adder cum subtractor using loop.vhd

   

library IEEE;
use IEEE.STD_LOGIC_1164.all;   
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity adder_subtractor_4bit is
     port(
         sel : in STD_LOGIC;
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end adder_subtractor_4bit;


architecture adder_subtractor_arc of adder_subtractor_4bit is
begin

    add_sub : process (a,b,sel) is
    variable l : std_logic_vector (3 downto 0) ;
    variable s : std_logic_vector (4 downto 0) ;   
    begin
        l := b xor (sel & sel & sel & sel);   
        s(0) := sel;
        for i in 0 to 3 loop
            dout(i) <= a(i) xor l(i) xor s(i);
            s(i+1) := (a(i) and l(i)) or (l(i) and s(i)) or (s(i) and a(i));
        end loop;
    end process add_sub;       

end adder_subtractor_arc;

Design of 4 Bit Subtractor using Loops (Behavior Modeling Style) (VHDL Code).






Design of 4 Bit Subtractor using Loops (Behavior Modeling Style).


Output Waveform :  4 Bit Subtractor




VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : subtractor_4bit
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : 4 bit subtractor using loops.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity subtractor_4bit is
     port(
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         diff : out STD_LOGIC_VECTOR(3 downto 0)
         );
end subtractor_4bit;


architecture subtractor_4bit_loop of subtractor_4bit is
begin

    sub4 : process (a,b) is
    variable l : std_logic_vector (3 downto 0) ;
    variable s : std_logic_vector (4 downto 0) ;
    begin
        l := not b;
        s(0) := '1';
        for i in 0 to 3 loop
            diff(i) <= a(i) xor l(i) xor s(i);
            s(i+1) := (a(i) and l(i)) or (l(i) and s(i)) or (s(i) and a(i));
        end loop;
    end process sub4;

end subtractor_4bit_loop;

Design of 4 Bit Adder using Loops (Behavior Modeling Style) (VHDL Code) -





Design of 4 Bit Adder using Loops (Behavior Modeling Style) -


Output Waveform  :   4 Bit Adder



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : adder_4
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : 4 bit adder using loop.vhd

   

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity adder_4 is
     port(
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         sum : out STD_LOGIC_VECTOR(4 downto 0)
         );
end adder_4;


architecture adder4_arc of adder_4 is
begin

    adder4 : process (a,b) is       
    variable s : std_logic_vector (4 downto 0);
    begin                                      
        s(0) := '0';
        for i in 0 to 3 loop
            sum(i) <= a(i) xor b(i) xor s(i) ;
            s(i+1) := (a(i) and b(i)) or (b(i) and s(i)) or (s(i) and a(i));
        end loop;                                                           
        sum(4) <= s(4);
    end process;

end adder4_arc;

Design of Stepper Motor Driver (Half Step) using Behavior Modeling Style (VHDL Code).





Design of Stepper Motor Driver (half step) using Behavior Modeling Style -


Output Waveform :   Stepper Motor Driver (Half Step).




VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : stepper_driver_half_step
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Stepper Motor Driver (half_step).vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity stepper_driver_half_step is
     port(
         clk : in STD_LOGIC;
         start : in STD_LOGIC;
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end stepper_driver_half_step;


architecture stepper_driver_arc of stepper_driver_half_step is
begin

    stepper_driver : process (clk,start) is
    variable m : std_logic_vector (2 downto 0) := "000";
    begin
        if (start='1') then
            if (rising_edge (clk)) then
                m := m + 1;
            end if;
        end if;
       
        case m is
            when "000" => dout <= "1000";
            when "001" => dout <= "1100";
            when "010" => dout <= "0100";
            when "011" => dout <= "0110";
            when "100" => dout <= "0010";
            when "101" => dout <= "0011";
            when "110" => dout <= "0001";
            when others => dout <= "1001";
        end case;
    end process stepper_driver;

end stepper_driver_arc;

Design of Stepper Motor Driver (Full Step) using Behavior Modeling Style (VHDL Code).






Design of Stepper Motor Driver (Full Step) using Behavior Modeling Style -


Output Waveform  :  Stepper Motor Driver (Full Step).



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : stepper_driver_full_step
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Stepper Motor Driver (full step).vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;       
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity stepper_driver_full_step is
     port(
         clk : in STD_LOGIC;
         start : in STD_LOGIC;
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end stepper_driver_full_step;


architecture stepper_driver_arc of stepper_driver_full_step is
begin

    stepper : process (clk,start) is
    variable m : std_logic_vector (1 downto 0) := "00";
    begin
        if (start='1') then
            if (rising_edge (clk)) then
                m := m + 1;
            end if;
        end if;
       
        case m is
            when "00" => dout <= "1000";  
            when "01" => dout <= "0100";
            when "10" => dout <= "0010";
            when others => dout <= "0001";
        end case;
    end process stepper;

end stepper_driver_arc;

Design of ODD number Frequency Divider using Behavior Modeling Style (VHDL Code).






Design of ODD number Frequency Divider using Behavior Modeling Style -

Output Waveform :  ODD number Frquency Divider



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : frequency_divider_odd
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : ODD numbers frequency divider (divide by 5).vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity frequency_divider_odd is
     port(
         clk : in STD_LOGIC;
         out_clk : out STD_LOGIC
         );
end frequency_divider_odd;


architecture frequency_divider_odd_arc of frequency_divider_odd is
begin

    frequency_divider : process (clk) is
    variable m : integer := 0;
    begin
        if (rising_edge (clk)) then
            m := m + 1;
        end if ;
        if (m=5) then
            m := 0;
        end if;
       
        if (m<3) then
            out_clk <= '1';
        else
            out_clk <= '0';
        end if;
    end process frequency_divider ;
       

end frequency_divider_odd_arc;

Design of 8 - nibble stack using Behavior Modeling Style (VHDL Code).






Design of 8-nibble STACK using Behavior Modeling Style -

Output Waveform :  8 nibble STACK Design



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : stack_8nibble
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of 4 bit stack using behavior modeling style.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;   
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity stack_8nibble is
     port(
         clk : in STD_LOGIC;
         push : in STD_LOGIC;
         pull : in STD_LOGIC;
         din : in STD_LOGIC_VECTOR(3 downto 0);       
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end stack_8nibble;


architecture stack_4nibble_arc of stack_8nibble is       

type mem is array (0 to 7) of std_logic_vector (3 downto 0);

signal stack : mem := (others=>(others=>'0'));

begin

    stack_design : process (clk,push,pull,din) is 
    variable i : integer := 0;
    begin
        if (rising_edge (clk)) then
            if (push='1') then
                stack(i) <= din;
                i := i+1;    
            elsif (pull='1') then
                i := i - 1;   
                dout <= stack(i);
            end if;       
        end if;
    end process stack_design;
               

end stack_4nibble_arc;

Design of First IN - Last OUT (FILO) Register using Behavior Modeling Style (VHDL Code).






Design of First IN - Last OUT (FILO) Register using Behavior Modeling Style -


Output Waveform :  First IN - Last OUT (FILO) Design



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : FILO
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of First In - Last Out Register.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FILO is
     port(
         load : in STD_LOGIC;
         clk : in STD_LOGIC;
         din : in STD_LOGIC_VECTOR (3 downto 0);
         dout : out STD_LOGIC
         );
end FILO;


architecture FILO_arc of FILO is
begin

    FILO_design : process (load,clk,din) is
    variable mem : std_logic_vector (3 downto 0) := (others=>'0');       
    variable i : integer range 0 to 3 := 0;
    begin
        if (load='1') then       
            mem := din;
        else
            if (rising_edge (clk)) then       
                dout <= mem(3);
                mem := mem(2 downto 0) & '0';
            end if;
        end if;
    end process FILO_design;
               

end FILO_arc;

Design of First IN - First OUT (FIFO) Register using Behavior Modeling Style (VHDL Code).






Design of First IN - First OUT  (FIFO)  Register using Behavior Modeling Style -


Output Waveform :   First IN - First OUT (FIFO) Register.



VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : FIFO
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of First In - First OUT Register.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FIFO is
     port(
         en : in STD_LOGIC;
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end FIFO;


architecture FIFO_arc of FIFO is
begin                   
   
    fifo_design : process (en,clk,din) is
    variable mem : std_logic_vector (3 downto 0) := (others => '0');
    begin
        if (en='1') then
            if (rising_edge (clk)) then
                dout <= mem(0);
                mem := (din & mem(3 downto 1));
            end if ;
        end if;
    end process fifo_design;
   

end FIFO_arc;

Design of 8 nibble RAM (Memory) using Behavior Modeling Style (VHDL Code) -






Design of 8 nibble RAM (Memory) using Behavior Modeling Style -


Output Waveform :   8 Nibble RAM (Memory)



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : RAM
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
--
-------------------------------------------------------------------------------
--
-- File        : Design of RAM (8 nibble) using behavior modeling style.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;   
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity RAM is
     port(
         en : in STD_LOGIC;
         nrw : in STD_LOGIC;
         addr : in STD_LOGIC_VECTOR(2 downto 0);
         din : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end RAM;


architecture RAM_arc of RAM is      

type memory is array (0 to 7) of std_logic_vector (3 downto 0);   

signal mem : memory := (0=>"1111",
1 => "1110",
2 => "1101",
3 => "1100",
4 => "1011",
5 => "1010",
6 => "1001",
7 => "1000");

begin

    memory_design : process (en,addr,nrw,din) is
    begin
        if (en='1') then
            if (nrw='0') then
                dout <= mem(conv_integer (addr));
            else
                mem (conv_integer (addr)) <= din;
            end if;
        end if;
    end process memory_design;

end RAM_arc;

 
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