A Small Discussion about VHDL & Verilog HDL -
|VHDL or Verilog HDL - A small discussion (VHDL with Naresh Singh Dobal learning Series).|
Verilog HDL is easier to understand and use, It is very effectively used for simulation and synthesis. but it lacks for system level or complex designing. It is promoted by OVI (Open Verilog International). It is widely used for ASIC designing or lower level design (RTL or lower), but this results in faster simulation and effective synthesis. Mostly used in North America, Asia & Japan, but not popular in Europe.
As comparable to verilog HDL, VHDL is more complex, thus difficult to learn and use. But this offers more flexibility of designing. Since VHDL is better suited for handling very complex systems, so it is now gaining popularity. VHDL is mainly promoted by VHDL international. VHDL is relatively weaker in lower designs. But superior in system level design. Many believes that in long terms presents better condition and adaptability than its competitors. This language is widely used in Europe, significantly used in US and Canada, but this disliked in Japan...
Both the HDL's are used to describe electronic systems.
The function of systems is to get input data from it's environment and give output some data in return.
In verilog HDL this is called a module which is a basic building block in Verilog HDL, and in VHDL this is defined in Entity & Architecture Pair.
Both the Languages are IEEE Standard.
I would love to read your suggestions and comments here below,
Best Regard //
Naresh Singh Dobal