Logical Operators test in VHDL Design

Basic Logical Gates Design using Data Flow Modelling Style (VHDL Code)-

Program --


-------------------------------------------------------------------------------
--
-- Title       : logical_gates
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : Logical Gate Test.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;   
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity logical_gates is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         c : out STD_LOGIC;
         d : out STD_LOGIC;
         e : out STD_LOGIC;
         f : out STD_LOGIC;
         g : out STD_LOGIC;
         h : out STD_LOGIC;
         i : out STD_LOGIC;
         j : out STD_LOGIC
         );
end logical_gates;

architecture logical_gates_arc of logical_gates is
begin

    c <= a and b;
    d <= a or b;
    e <= not a;
    f <= not b;
    g <= a nand b;
    h <= a nor b;
    i <= a xor b;
    j <= a xnor b;

end logical_gates_arc;