Sunday, 14 July 2013

Half Subtractor Design using Logical Expression (VHDL Code).

Half Subtractor Design using Logical Expression (VHDL Code).


Output Waveform : Half Subtractor


Program-


-------------------------------------------------------------------------------
--
-- Title       : half_subtractor
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity half_subtractor is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         diff : out STD_LOGIC;
         borrow : out STD_LOGIC
         );
end half_subtractor;

architecture half_subtractor_arc of half_subtractor is
begin

    diff <= a xor b;
    borrow <= (not a) and b;

end half_subtractor_arc;

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