Sunday, 14 July 2013

Half Adder Design using Logical Expressions (VHDL Code)


Half Adder Design Using Logical Expressions (VHDL Code)-



















Program-



-------------------------------------------------------------------------------
--
-- Title       : Half_Adder
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Half_Adder is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         sum : out STD_LOGIC;
         carry : out STD_LOGIC
         );
end Half_Adder;

architecture Half_Adder_arc of Half_Adder is
begin

    sum <= a xor b;
    carry <= a and b;

end Half_Adder_arc;

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