Sunday, 14 July 2013

Full Subtractor Design using Logical Gates (VHDL Code).

Full Subtractor Design using Logical Gates (VHDL Code)-


Output Waveform : Full Subtractor

Program-


-------------------------------------------------------------------------------
--
-- Title       : full_subtractor
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity full_subtractor is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         c : in STD_LOGIC;
         difference : out STD_LOGIC;
         borrow : out STD_LOGIC
         );
end full_subtractor;

architecture full_subtractor_arc of full_subtractor is
begin

    difference <= a xor b xor c;
    borrow <= ((not a) and b) or
               (b and c) or
               (c and (not a));

end full_subtractor_arc;
 

2 comments :

Venkatesh Kaduru said...

please can you write with 2 inputs

Unknown said...

if we write 2 input it act like full subtractor

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