Sunday, 14 July 2013

Full Adder Design using Logical Expression (VHDL Code).

Full Adder Desing using Logical Expression (VHDL Code) 

Output Waveform of Full Adder

VHDL Code  (Data Flow Modelling Style) -


-------------------------------------------------------------------------------
--
-- Title       : Full_Adder_Design
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Full_Adder_Design is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         c : in STD_LOGIC;
         sum : out STD_LOGIC;
         carry : out STD_LOGIC
         );
end Full_Adder_Design;

architecture Full_Adder_Design_arc of Full_Adder_Design is
begin

    sum <= a xor b xor c;
    carry <= (a and b) or               
             (b and c) or
             (c and a);
           
end Full_Adder_Design_arc;

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