Wednesday, 17 July 2013

Design of Toggle Flip Flop using D-Flip Flop (VHDL Code).




Design of Toggle Flip Flop using D-Flip Flop (Structural Modeling Style) -



Output Waveform : T flip flop


VHDL Code-


-------------------------------------------------------------------------------
--
-- Title       : tff_using_dff
-- Design      : verilog upload
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : Design of Toggle Flip Flop using DFF.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity tff_using_dff is
     port(
         clk : in STD_LOGIC;
         t : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end tff_using_dff;

architecture tff_using_dff_arc of tff_using_dff is   

component d_flip_flop is
     port(
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end component d_flip_flop;

signal ip : std_logic;
signal op : std_logic;   

begin
   
    ip <= op xor t ;
    u0 : d_flip_flop port map (clk => clk,
                            din => ip,
                            reset => reset,
                            dout => op);
   
    dout <= op;


end tff_using_dff_arc;





-------------------- D Flip Flop Design ---------------------



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity d_flip_flop is
     port(
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end d_flip_flop;

architecture d_flip_flop_arc of d_flip_flop is   
begin
   
    dff : process (din,clk,reset) is
    begin
        if (reset='1') then
            dout <= '0';
        elsif (rising_edge (clk)) then
            dout <= din;
        end if;
    end process dff;


end d_flip_flop_arc;

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