Monday, 29 July 2013

Design of Parallel In - Serial OUT Shift Register using Behavior Modeling Style (VHDL Code).






Design of Parallel IN - Serial OUT Shift Register using Behavior Modeling Style -

Output Waveform : Parallel IN - Serial OUT Shift Register





VHDL Code-




-------------------------------------------------------------------------------
--
-- Title       : parallel_in_serial_out
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Parallel IN - Serial OUT Shift Register.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity parallel_in_serial_out is
     port(
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         load : in STD_LOGIC;
         din : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC
         );
end parallel_in_serial_out;


architecture piso_arc of parallel_in_serial_out is
begin

    piso : process (clk,reset,load,din) is
    variable temp : std_logic_vector (din'range);
    begin
        if (reset='1') then
            temp := (others=>'0');
        elsif (load='1') then
            temp := din ;
        elsif (rising_edge (clk)) then
            dout <= temp(3);
            temp := temp(2 downto 0) & '0';
        end if;
    end process piso;

end piso_arc;

4 comments :

Rizkinya Rizki said...

Hello Sir, if I want to increase the input of PISO to 8 inputs (0 to 7), where the code that I must modify...?

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity parallel_in_serial_out is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
load : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(7 downto 0);
dout : out STD_LOGIC
);
end parallel_in_serial_out;


architecture piso_arc of parallel_in_serial_out is
begin

piso : process (clk,reset,load,din) is
variable temp : std_logic_vector (din'range);
begin
if (reset='1') then
temp := (others=>'0');
elsif (load='1') then
temp := din ;
elsif (rising_edge (clk)) then
dout <= temp(7);
temp := temp(6 downto 0) & '0';
end if;
end process piso;

end piso_arc;

thank you

Elda said...

how to design a series piso ??

'cinema'd creations said...

how to write a vhdl code for push in bus out shift register?

Nur Haque said...

Thanks for nice post.C programming details here

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