Wednesday, 17 July 2013

Design of Parallel IN - Parallel OUT Shift Register using D-Flip Flop (VHDL Code).





Design of   Parallel  IN   -  Parallel  OUT   Shift Register using D- Flip Flop (Structural Modeling Style)-



Output Waveform    :   Parallel IN   Parallel OUT   Shift Register



VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : pipo
-- Design      : upload_design1
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : Design of Parallel in  -  parallel out using d_flip_flop.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity pipo is
     port(
         din : in STD_LOGIC_VECTOR (3 downto 0);
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end pipo;

architecture pipo_arc of pipo is  

component d_flip_flop is
     port(
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end component d_flip_flop;   


begin
   
    u0 : d_flip_flop port map (clk => clk,
                                din => din(0),
                                reset => reset,
                                dout => dout(0));
   
    u1 : d_flip_flop port map (clk => clk,
                                din => din(1),
                                reset => reset,
                                dout => dout(1));
   
    u2 : d_flip_flop port map (clk => clk,
                                din => din(2),
                                reset => reset,
                                dout => dout(2));
   
    u3 : d_flip_flop port map (clk => clk,
                                din => din(3),
                                reset => reset,
                                dout => dout(3));   
              

end pipo_arc;      



-------------------- D Flip Flop Design ---------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity d_flip_flop is
     port(
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end d_flip_flop;

architecture d_flip_flop_arc of d_flip_flop is   

begin
   
    dff : process (din,clk,reset) is
    begin
        if (reset='1') then
            dout <= '0';
        elsif (rising_edge (clk)) then
            dout <= din;
        end if;
    end process dff;


end d_flip_flop_arc;

2 comments :

ahmed yahya said...

thank you so much that was really helpful :)

Anonymous said...

Hey, thank you for the codes. I think that you should not include din in the sensitivity list of the process, otherwise the synthesizer could understand that you want a latch. The process should only activate when there is a change in clk or reset. Cheers!

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