Saturday, 27 July 2013

Design of ODD number Frequency Divider using Behavior Modeling Style (VHDL Code).






Design of ODD number Frequency Divider using Behavior Modeling Style -

Output Waveform :  ODD number Frquency Divider



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : frequency_divider_odd
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : ODD numbers frequency divider (divide by 5).vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity frequency_divider_odd is
     port(
         clk : in STD_LOGIC;
         out_clk : out STD_LOGIC
         );
end frequency_divider_odd;


architecture frequency_divider_odd_arc of frequency_divider_odd is
begin

    frequency_divider : process (clk) is
    variable m : integer := 0;
    begin
        if (rising_edge (clk)) then
            m := m + 1;
        end if ;
        if (m=5) then
            m := 0;
        end if;
       
        if (m<3) then
            out_clk <= '1';
        else
            out_clk <= '0';
        end if;
    end process frequency_divider ;
       

end frequency_divider_odd_arc;

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