Saturday, 27 July 2013

Design of ODD Counter using FSM Technique. (VHDL Code).





Design of ODD Counter using FSM Technique -


Output Waveform :  3 Bit ODD Counter.



VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : odd_counter_using_fsm
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : ODD Counter Design using FSM Technique.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity odd_counter_using_fsm is
     port(
         clk : in STD_LOGIC;
         dout : out STD_LOGIC_VECTOR(2 downto 0)
         );
end odd_counter_using_fsm;


architecture odd_counter_arc of odd_counter_using_fsm is  

type state is (st1,st2,st3,st4) ;

signal p_state : state;
signal n_state : state;       

begin
   
    present_state : process (clk) is
    begin
        if (rising_edge (clk)) then
            p_state <= n_state;
        end if;
    end process present_state;
   
   
    next_state : process (p_state) is
    begin
        case (p_state) is
            when st1 =>
            n_state <= st2;
            dout <= "001";
            when st2 =>
            n_state <= st3;
            dout <= "011";
            when st3 =>
            n_state <= st4;
            dout <= "101";
            when st4 =>
            n_state <= st1;
            dout <= "111";
        end case;
    end process next_state;
           


end odd_counter_arc;

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