Monday, 22 July 2013

Design of MOD-6 Counter using Behavior Modeling Style (VHDL Code).






Design of MOD-6 Counter using Behavior Modeling Style -


  
Output Waveform :   MOD-6 Counter



VHDL Code-



-------------------------------------------------------------------------------
--
-- Title       : mod6_counter
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : mod - 6 counter.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mod6_counter is
     port(
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC_VECTOR(2 downto 0)
         );
end mod6_counter;

architecture mod6_counter_arc of mod6_counter is
begin

    counter : process (clk,reset) is
    variable m : integer range 0 to 7 := 0;
    begin
        if (reset='1') then
            m := 0;
        elsif (rising_edge (clk)) then
            m := m + 1;
        end if;
        if (m=6) then
            m := 0;
        end if;
        dout <= conv_std_logic_vector (m,3);
    end process counter;

end mod6_counter_arc;

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