Wednesday, 17 July 2013

Design of Master - Slave Flip Flop using D- Flip Flop (VHDL Code).





Design of Master - Slave Flip Flop using D- Flip Flop (Structural Modeling Style) -


Output Waveform :   Master   Slave  Flip Flop


VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : master_slave_ff
-- Design      : verilog upload
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : Design of Master Slave Flip Flop using D-Flip Flop.vhd




library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity master_slave_ff is
     port(
         din : in STD_LOGIC;
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end master_slave_ff;

architecture master_slave_ff_arc of master_slave_ff is

component d_flip_flop is
     port(
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end component d_flip_flop;     

signal s : std_logic ;
signal in_clk : std_logic;

begin         
   
    in_clk <= not clk;
   
    u0 : d_flip_flop port map (clk => clk,
                                din => din ,
                                reset => reset ,
                                dout => s);
                           
     u1 : d_flip_flop port map (clk => in_clk,
                                din => s ,
                                reset => reset ,
                                dout => dout);
   

end master_slave_ff_arc;




-------------------- D Flip Flop Design ---------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity d_flip_flop is
     port(
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end d_flip_flop;

architecture d_flip_flop_arc of d_flip_flop is   

begin
   
    dff : process (din,clk,reset) is
    begin
        if (reset='1') then
            dout <= '0';
        elsif (rising_edge (clk)) then
            dout <= din;
        end if;
    end process dff;


end d_flip_flop_arc;

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