Saturday, 20 July 2013

Design of JK Flip Flop using Behavior Modeling Style (VHDL Code).






Design of JK Flip Flop using Behavior Modeling Style -



Output Waveform :   JK Flip Flop




VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : jk_flip_flop
-- Design      : vhdl_upload 1
-- Author      : Naresh Singh Dobal
-- Company     : nsd
-- VHDL Tutorials & exercise by Naresh Singh Dobal
--
-------------------------------------------------------------------------------
--
-- File        : JK Flip Flop.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity jk_flip_flop is
     port(
         j : in STD_LOGIC;
         k : in STD_LOGIC;
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         q : out STD_LOGIC;
         qb : out STD_LOGIC
         );
end jk_flip_flop;

architecture jk_flip_flop_arc of jk_flip_flop is
begin

    jkff : process (j,k,clk,reset) is
    variable m : std_logic := '0';
    begin
        if (reset='1') then
            m := '0';
        elsif (rising_edge (clk)) then
            if (j/=k) then
                m := j;
            elsif (j='1' and k='1') then
                m := not m;
            end if;
        end if;
        q <= m;
        qb <= not m;
    end process jkff;
   

end jk_flip_flop_arc;

10 comments :

Mukul Raj said...

BY adding _ with every word ,you have made this program little more complexed .It can be made very simple.The way u have represented the inputs it can be programmed in single line as
(j,k,clk,reset:in std_logic);

naresh.dobal said...

Yes, there is no doubt that you can write all inputs in single line, But these are the simple programs, so you can easily memorized the inputs and there function, but if you go with complex systems, where a Designing team working on the different different segments and modules, single line declaration results in many confusions and difficult to structured, where as in multiline declaration you can easily distinguish all inputs , So always make a better way of working and make it in your practice to be a good engineer.

Abhishek Bansal said...

Signal m cannot be synthesized, bad synchronous description.:error
in jk flip flop beh. modelling using if statement

Electric Guy said...

The output for the following toggle case will only always be '1', as in the process, the variable is set as '0' whenever initialized.
if(j = '1' and k = '1') then
m: not m;

A better solutions to this problem is as below:

Architecture Behavioral of jk_flip_flop is

signal w: std_logic:='0';

begin

Q <= w;
Qb <= not w;

jk_ff_process: process(J,K,CLK,RESET)

begin
if(RESET = 1) then
w <= '0';
end if;

if(rising_edge(CLK) then

if(J = '1' and K = '0') then
w <= '1';
end if;


if(J = '0' and K = '1') then
w <= '0';
end if;

if(w = '1' and J = '1' and K = '1') then
w <= '0';
end if;

if(w = '0' and J = '1' and K = '1') then
w <= '1';
end if;

end if;

end process jk_ff_process;

end Behavioral;


Aashish Atrey said...

how to make jk flip flop coding by case statement in behavioural style of modelling

Shashank Sinha said...

i'm writing vhdl code of jk flipflop using dataflow model, but when i run the program it shows an error "iteration limit reached, see the manual".

godfather said...

how do you give the inputs after adding the signals to the wave?

godfather said...

how do you give the inputs after adding the signals to the wave?

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Hansi Yashodhara said...

How to write VHDL code to implement mod 8 counter

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