Monday, 22 July 2013

Design of Integer counter using Behavior Modeling Style. (VHDL Code).






Design of Integer Counter using Behavior Modeling Style -



Output Waveform :   Integer Counter



VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : counter_integer
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : integer counter.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter_integer is
     port(
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC_VECTOR(9 downto 0)
         );
end counter_integer;


architecture counter_arc of counter_integer is
begin

    count : process (clk,reset) is
    variable m : integer range 0 to 1023 := 0;
    begin
        if (reset='1') then
            m := 0;
        elsif (rising_edge (clk)) then
            m := m + 1;
        end if;       
        if (m=1023) then
            m := 0;
        end if;
        dout <= conv_std_logic_vector (m,10);
    end process count;

end counter_arc;

1 comments :

Anonymous said...

Your doing great job
keep it.............

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