Monday, 22 July 2013

Design of Frequency Divider (Divide by 10) using Behavior Modeling Style (VHDL Code).







Design of Frequency Divider  (Divide by 10) using Behavior Modeling Style -


Output Waveform :    Frequency Divider (Divide by 10) .




VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : frequency_divider_by10
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : frequency divider by 10.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity frequency_divider_by10 is
     port(
         clk : in STD_LOGIC;
         out_clk : out STD_LOGIC
         );
end frequency_divider_by10;


architecture frequency_divider_by10_arc of frequency_divider_by10 is
begin

    divider : process (clk) is
    variable m : integer range 0 to 15 := 0;
    begin
        if (rising_edge (clk)) then
            m := m + 1;
        end if;
       
        if (m=10) then
            m := 0;
        end if;
       
        if (m<5) then
            out_clk <= '1';
        else
            out_clk <= '0';
        end if;
    end process divider;

end frequency_divider_by10_arc;

2 comments :

Carlos Ramos said...

Hey, Naresh,
I have also implemented a frequency divider, although I used a signal declared in the architecture rather than a variable in the process.

Is there any performance difference from using VARIABLE or SIGNAL? Is there any recommended way? I though variables should be avoided if not needed, and stick most possible with vectors and signals.

In the end, both my signal or your variable are integer in type, but I am not sure of how synthesis implements each. Is there any documentation you can provide on the matter?

Regards.

Unknown said...

Hey signals and variables are very different. Signals are declared outside the process block but can be used in processes as well. Variables are however declared inside the process and are local only to that process.
The major difference however is the time taken. Signals take a delta time to be assigned after calculations. While variables are assigned instantaneously. Signals create a lot of delay, hence a lot of problems too if used in the process block in complex programs. Try using variables in sequential modelling. Avoid using signals here.
However signals are used only for port mapping in structural coding as variables are local and cannot be used , and also because port mapping is done in behavioural modelling method. Hope I answered your question.

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