Monday, 22 July 2013

Design of Frequency Divider (Divide by 4) using Behavior Modeling Style (VHDL Code).






Design of Frequency Divider (divide by 4) using Behavior Modeling Style -


Output Waveform  :    Frequency Divider (Divide by 4).




VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : frequency_divider_by4
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : frequency divider by 4.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;   
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity frequency_divider_by4 is
     port(
         clk : in STD_LOGIC;
         out_clk : out STD_LOGIC
         );
end frequency_divider_by4;


architecture frequency_divider_by4_arc of frequency_divider_by4 is
begin

    divider : process (clk) is
    variable m : std_logic_vector (1 downto 0) := "00";
    begin
        if (rising_edge (clk)) then
            m := m + 1;
        end if;
        out_clk <= m(1);
    end process divider;
   

end frequency_divider_by4_arc;

2 comments :

ankscool said...

is there any other way of writing the above program...i wrote my program somewhat like ....it is not working !!!!
architecture Behavioral of freq_4div is

begin
divider:process(clk)
variable m: std_logic :='0' ;
begin
if (rising_edge(clk)) then
m:=m+1;
if (m:='4') then
m:= '0' ;
end if;
if (m < 2) then
out_clk<='1' ;
else
out_clk<='0' ;
end if;
end process;


end Behavioral;

Alok Kumar said...

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity frequency_divider_by4 is
port(
clk : in STD_LOGIC;
out_clk : out STD_LOGIC
);
end frequency_divider_by4;


architecture frequency_divider_by4_arc of frequency_divider_by4 is
begin

divider : process (clk) is
variable m : integer range 0 to 3 := 0;
variable n : std_logic := '0';
begin
if (rising_edge (clk)) then
m := m + 1;
if (m = 3) then
m := 0;
n := not n;
end if ;

end if;
out_clk <= n;
end process divider;


end frequency_divider_by4_arc;

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