Saturday, 27 July 2013

Design of First IN - Last OUT (FILO) Register using Behavior Modeling Style (VHDL Code).






Design of First IN - Last OUT (FILO) Register using Behavior Modeling Style -


Output Waveform :  First IN - Last OUT (FILO) Design



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : FILO
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of First In - Last Out Register.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity FILO is
     port(
         load : in STD_LOGIC;
         clk : in STD_LOGIC;
         din : in STD_LOGIC_VECTOR (3 downto 0);
         dout : out STD_LOGIC
         );
end FILO;


architecture FILO_arc of FILO is
begin

    FILO_design : process (load,clk,din) is
    variable mem : std_logic_vector (3 downto 0) := (others=>'0');       
    variable i : integer range 0 to 3 := 0;
    begin
        if (load='1') then       
            mem := din;
        else
            if (rising_edge (clk)) then       
                dout <= mem(3);
                mem := mem(2 downto 0) & '0';
            end if;
        end if;
    end process FILO_design;
               

end FILO_arc;

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