Saturday, 20 July 2013

Design of D-Latch using Behavior Modeling Style (VHDL Code).






Design of D-Latch using Behavior Modeling Style-



Output Waveform :   D - Latch



VHDL Code -




-------------------------------------------------------------------------------
--
-- Title       : D_latch
-- Design      : vhdl_upload 1
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Tutorials & exercise by Naresh Singh Dobal
--
-------------------------------------------------------------------------------
--
-- File        : D Latch using Behavior Modeling Style.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity D_latch is
     port(
         enable : in STD_LOGIC;
         din : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end D_latch;

architecture D_latch_arc of D_latch is
begin

    latch : process (enable,din,reset) is
    begin
        if (reset='1') then
            dout <= '0';
        elsif (enable='1') then
            dout <= din;
        end if;
    end process latch;

end D_latch_arc;

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