Saturday, 20 July 2013

Design of D Flip Flop Using Behavior Modeling Style (VHDL Code).







Design of D Flip Flop using Behavior Modeling Style -



Output Waveform :   D- Flip Flop




VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : d_flip_flop
-- Design      : vhdl_upload 1
-- Author      : Naresh Singh Dobal
-- Company     : nsd 
-- VHDL Tutorials & exercise by Naresh Singh Dobal
--
-------------------------------------------------------------------------------
--
-- File        : D flip flop.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity d_flip_flop is
     port(
         din : in STD_LOGIC;
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end d_flip_flop;

architecture d_flip_flop_arc of d_flip_flop is
begin

    dff : process (din,clk,reset) is
    begin
        if (reset='1') then
            dout <= '0';
        elsif (rising_edge (clk)) then
            dout <= din;
        end if;
    end process dff;

end d_flip_flop_arc;

3 comments :

Anonymous said...

undefined output for fist clock cycle. WHY?

Nur Haque said...

Thanks for nice post.C programming details here

Anonymous said...

Thank u so much!!!

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