Monday, 22 July 2013

Design of BCD Counter using Behavior Modeling Style. (VHDL Code)






Design of BCD Counter using Behavior Modeling Style -



Output Waveform :    BCD Counter



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : bcd_counter
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : BCD Counter.vhd




library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity bcd_counter is
     port(
         reset : in STD_LOGIC;
         clk : in STD_LOGIC;
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end bcd_counter;


architecture bcd_counter_arc of bcd_counter is
begin

    count : process (reset,clk) is
    variable m : std_logic_vector (3 downto 0) := "0000";
    begin
        if (reset='1') then
            m := "0000";
        elsif (rising_edge (clk)) then
            m := m + 1;
        end if;         
        if (m="1010") then
            m := "0000";
        end if;
        dout <= m;
    end process count;

end bcd_counter_arc;

6 comments :

Anonymous said...

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Saurabh Kaushik said...

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