Saturday, 27 July 2013

Design of 8 - nibble stack using Behavior Modeling Style (VHDL Code).






Design of 8-nibble STACK using Behavior Modeling Style -

Output Waveform :  8 nibble STACK Design



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : stack_8nibble
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of 4 bit stack using behavior modeling style.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;   
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity stack_8nibble is
     port(
         clk : in STD_LOGIC;
         push : in STD_LOGIC;
         pull : in STD_LOGIC;
         din : in STD_LOGIC_VECTOR(3 downto 0);       
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end stack_8nibble;


architecture stack_4nibble_arc of stack_8nibble is       

type mem is array (0 to 7) of std_logic_vector (3 downto 0);

signal stack : mem := (others=>(others=>'0'));

begin

    stack_design : process (clk,push,pull,din) is 
    variable i : integer := 0;
    begin
        if (rising_edge (clk)) then
            if (push='1') then
                stack(i) <= din;
                i := i+1;    
            elsif (pull='1') then
                i := i - 1;   
                dout <= stack(i);
            end if;       
        end if;
    end process stack_design;
               

end stack_4nibble_arc;

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