Saturday, 27 July 2013

Design of 8 Nibble ROM (Memory) using Behavior Modeling Style (VHDL Code).






Design of 8 Nibble ROM (Memory) using Behavior Modeling Style -


Output Waveform :   ROM (memory) (8 nibble).



VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : ROM
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of ROM (8 nibble) using Behavior Modeling Style.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ROM is
     port(
         en : in STD_LOGIC;
         addr : in STD_LOGIC_VECTOR(2 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end ROM;

architecture ROM_arc of ROM is     

type memory is array (0 to 7) of std_logic_vector (3 downto 0);   

signal mem : memory := (0=>"1111",
1 => "1110",
2 => "1101",
3 => "1100",
4 => "1011",
5 => "1010",
6 => "1001",
7 => "1000");

begin

    memory_design : process (en,addr) is
    begin
        if (en='1') then
            dout <= mem(conv_integer (addr));
        end if;
    end process memory_design;
   

end ROM_arc;

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