Monday, 29 July 2013

Design of 8 nibble Queue using Behavior Modeling Style (VHDL Code).






Design of 8 nibble Queue using Behavior Modeling STyle -


Output Waveform :  8 nibble queue design



VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : queue_8nibble
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of 8 nibble queue using Behavior Modeling Style.vhd



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity queue_8nibble is
     port(
         clk : in STD_LOGIC;
         push : in STD_LOGIC;
         pull : in STD_LOGIC;
         din : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end queue_8nibble;


architecture queue_8nibble_arc of queue_8nibble is

type mem is array (0 to 7) of std_logic_vector (3 downto 0);

signal queue : mem := (others=>(others=>'0'));

begin

    queue_design : process (clk,push,pull,din) is   
    variable mem : std_logic_vector (3 downto 0) ;
    variable i : integer := 0;
    begin                   
        if (rising_edge (clk)) then
            if (push='1') then
                queue(i) <= din;  
                if (i<7) then
                    i := i + 1;       
                end if;
            elsif (pull='1') then   
                dout <= queue(0); 
                if (i>0) then
                    i := i - 1;
                end if;
                queue(0 to 6) <= queue(1 to 7);
            end if;
        end if;
    end process queue_design;
   

end queue_8nibble_arc;

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