Saturday, 20 July 2013

Design of 4 to 2 Encoder using CASE Statements (VHDL Code).






Design of 4 to 2 Encoder using CASE Statements (Behavior Modeling Style).


Output Waveform :   4 to 2 Encoder




VHDL Code-



-------------------------------------------------------------------------------
--
-- Title       : encoder_case
-- Design      : vhdl_upload 1
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Tutorials & exercise by Naresh Singh Dobal
-------------------------------------------------------------------------------
--
-- File        : 4 to 2 encoder using case.vhd

   

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity encoder_case is
     port(
         din : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC_VECTOR(1 downto 0)
         );
end encoder_case;


architecture encoder_case_arc of encoder_case is
begin

    encoder : process (din) is
    begin
        case din is
            when "1000" => dout <= "00";
            when "0100" => dout <= "01";
            when "0010" => dout <= "10";
            when "0001" => dout <= "11";
            when others => dout <= "ZZ";
        end case;
    end process encoder;

end encoder_case_arc;

1 comments :

Unknown said...

I want this in verilog

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