Saturday, 20 July 2013

Design of 4 to 1 Multiplexer using CASE Statement (VHDL Code).





Design of 4 to 1 Multiplexer using CASE Statement (Behavior Modeling Style) -



Output Waveform :   4 to 1 Multiplexer


VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : multiplexer_case
-- Design      : vhdl_upload 1
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Tutorials & exercise by Naresh Singh Dobal
-------------------------------------------------------------------------------
--
-- File        : 4 to 1 multiplexer using case.vhd

   

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity multiplexer_case is
     port(
         din : in STD_LOGIC_VECTOR(3 downto 0);
         sel : in STD_LOGIC_VECTOR(1 downto 0);
         dout : out STD_LOGIC
         );
end multiplexer_case;


architecture multiplexer_case_arc of multiplexer_case is
begin

    mux : process (din,sel) is
    begin
        case sel is
            when "00" => dout <= din(3);
            when "01" => dout <= din(2);
            when "10" => dout <= din(1);
            when others => dout <= din(0);
        end case;
    end process mux;

end multiplexer_case_arc;

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