Saturday, 20 July 2013

Design of 4 Bit Serial IN - Parallel OUT Shift Register using Behavior Modeling Style (VHDL Code).






Design of 4 Bit Serial IN - Parallel OUT Shift Register uisng Behavior Modeling Style -



Output Waveform :   Serial IN - Parallel OUT Shift Register



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : sipo_behavior
-- Design      : vhdl_upload 1
-- Author      : Naresh Singh Dobal
-- Company     : nsd 
-- VHDL Tutorials & exercise by Naresh Singh Dobal
--
-------------------------------------------------------------------------------
--
-- File        : serial in parallel out using behavior modeling style.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity sipo_behavior is
     port(
         din : in STD_LOGIC;
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end sipo_behavior;

architecture sipo_behavior_arc of sipo_behavior is
begin

     sipo : process (clk,din,reset) is
    variable s : std_logic_vector(3 downto 0) := "0000" ;
    begin
        if (reset='1') then
            s := "0000";
        elsif (rising_edge (clk)) then      
            s := (din & s(3 downto 1));   
        end if;      
        dout <= s;
    end process sipo;

end sipo_behavior_arc;

5 comments :

Anonymous said...

these are very useful codes which i never found in others sites but bro please try to write test bench also for each code .

Anonymous said...

there is an error in the header file. no idea why?

Anonymous said...

what is the meaning of line s := (din & s(3 downto 1));

Anonymous said...

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity sipo_behavior is
port(
din : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end sipo_behavior;

architecture sipo_behavior_arc of sipo_behavior is
begin

sipo : process (clk,din,reset) is
variable s : std_logic_vector(3 downto 0) := "0000" ;
begin
if (reset='1') then
s := "0000";
elsif (rising_edge (clk)) then
for i in 0 to 2 loop
s(i+1) := s(i);
end loop
end if;
dout <= s;
end process sipo;

end sipo_behavior_arc;

whats wrong with this code??

sandi kilo said...

end loop
char ; is missing => end loop;

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