Saturday, 27 July 2013

Design of 4 Bit Adder using Loops (Behavior Modeling Style) (VHDL Code) -





Design of 4 Bit Adder using Loops (Behavior Modeling Style) -


Output Waveform  :   4 Bit Adder



VHDL Code -


-------------------------------------------------------------------------------
--
-- Title       : adder_4
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : 4 bit adder using loop.vhd

   

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity adder_4 is
     port(
         a : in STD_LOGIC_VECTOR(3 downto 0);
         b : in STD_LOGIC_VECTOR(3 downto 0);
         sum : out STD_LOGIC_VECTOR(4 downto 0)
         );
end adder_4;


architecture adder4_arc of adder_4 is
begin

    adder4 : process (a,b) is       
    variable s : std_logic_vector (4 downto 0);
    begin                                      
        s(0) := '0';
        for i in 0 to 3 loop
            sum(i) <= a(i) xor b(i) xor s(i) ;
            s(i+1) := (a(i) and b(i)) or (b(i) and s(i)) or (s(i) and a(i));
        end loop;                                                           
        sum(4) <= s(4);
    end process;

end adder4_arc;

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