Monday, 15 July 2013

Design of 4 : 2 Encoder using with-select Concurrent Statement (VHDL Code).

Design of 4 : 2 Encoder using with - select concurrent statement (Data Flow Modeling Style)-


Output Waveform : 4 : 2 Encoder


VHDL Code-


-------------------------------------------------------------------------------
--
-- Title       : encoder4_2
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
--
-- File        : 4 : 2 Encoder using with select.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity encoder4_2 is
     port(
         din : in STD_LOGIC_VECTOR(3 downto 0);
         dout : out STD_LOGIC_VECTOR(1 downto 0)
         );
end encoder4_2;

architecture encoder4_2_arc of encoder4_2 is
begin

    with din select
    dout <= "00" when "1000",
            "01" when "0100",
            "10" when "0010",
            "11" when "0001",
            "ZZ" when others;
   
end encoder4_2_arc;

2 comments :

Unknown said...

what about the enable signal ?

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