Saturday, 20 July 2013

Design of 2 to 4 Decoder using CASE Statements (VHDL Code).





Design of 2 to 4 Decoder using  CASE Statements (Behavior Modeling Style)-



Output Waveform :   2 to 4 Decoder




VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : decoder_case
-- Design      : vhdl_upload 1
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Tutorials & exercise by Naresh Singh Dobal
-------------------------------------------------------------------------------
--
-- File        : 2 to 4 decoder using case.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity decoder_case is
     port(
         din : in STD_LOGIC_VECTOR(1 downto 0);
         dout : out STD_LOGIC_VECTOR(3 downto 0)
         );
end decoder_case;


architecture decoder_case_arc of decoder_case is
begin

    decoder : process (din) is
    begin
        case din is
            when "00" => dout <= "1000";
            when "01" => dout <= "0100";
            when "10" => dout <= "0010";
            when others => dout <= "0001";
        end case;
    end process decoder;

end decoder_case_arc;

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