Monday, 22 July 2013

Design of 2 Bit Binary Counter using Behavior Modeling Style (VHDL Code).






Design of 2 Bit Binary Counter using Behavior Modeling Style -


Output Waveform :  2 Bit Binary Counter.




VHDL Code -



-------------------------------------------------------------------------------
--
-- Title       : counter_2bit
-- Design      : vhdl_upload2
-- Author      : Naresh Singh Dobal
-- Company     : nsdobal@gmail.com
-- VHDL Programs &  Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File        : Design of 2 bit counter using behavior modeling style.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;  
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity counter_2bit is
     port(
         clk : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC_VECTOR(1 downto 0)
         );
end counter_2bit;

architecture counter_2bit_arc of counter_2bit is
begin

    counting : process (clk,reset) is
    variable m : std_logic_vector (1 downto 0) := "00";
    begin
        if (reset='1') then
            m := "00";
        elsif (rising_edge (clk)) then
            m := m + 1;
        end if;
        dout <= m;
    end process counting;

end counter_2bit_arc;

4 comments :

GeekProgrammer said...

This code is not working.
Its showing error in m:=m + 1;

Anonymous said...

of course it does no work...m is declared as a signal not as a variable...the code in general is false

Anonymous said...

sorry wrong...m is declared as a variable but is being treated as signal at one point

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