Sunday, 14 July 2013

Design of 1 Bit Comparator using Logical Gates (VHDL Code).

Design of 1 Bit Comparator using Logical Gates (VHDL Code)-


Output Waveform : 1 Bit Comparator


Program-


-------------------------------------------------------------------------------
--
-- Title       : comparator
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity comparator is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         equal : out STD_LOGIC;
         lower : out STD_LOGIC;
         greater : out STD_LOGIC
         );
end comparator;

architecture comparator_arc of comparator is
begin

    equal <= a xnor b;
    lower <= (not a) and b;
    greater <= a and (not b);

end comparator_arc;

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