Sunday, 14 July 2013

4 : 2 Encoder using Logical Gates (VHDL Code).

4 : 2 Encoder Design using Logical Gates (Data Flow Modelling Style). (VHDL Code)-



Output Waveform - 4 : 2 Encoder


Program -


-------------------------------------------------------------------------------
--
-- Title       : encoder4_2
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity encoder4_2 is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         c : in STD_LOGIC;
         d : in STD_LOGIC;
         x : out STD_LOGIC;
         y : out STD_LOGIC
         );
end encoder4_2;
                                           
architecture encoder4_2_arc of encoder4_2 is
begin

    x <= b or d;
    y <= c or d;

end encoder4_2_arc;



1 comments :

ANKUSH GARG said...

i think it is wrong...will u please check it

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