Sunday, 14 July 2013

2 : 4 Decoder using Logical GATES (VHDL Code).

2 : 4 Decoder Design using Logical Gates (Data Flow Modelling Style). (VHDL Code).

Output Waveform for 2 : 4 Decoder


Program-

-------------------------------------------------------------------------------
--
-- Title       : decoder2_4
-- Design      : vhdl_test
-- Author      : Naresh Singh Dobal
-- Company     : nsd
--
-------------------------------------------------------------------------------
                                     
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity decoder2_4 is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         w : out STD_LOGIC;
         x : out STD_LOGIC;
         y : out STD_LOGIC;
         z : out STD_LOGIC
         );
end decoder2_4;

architecture decoder2_4_arc of decoder2_4 is
begin

    w <= (not a) and (not b);
    x <= (not a) and b;
    y <= (a and (not b));
    z <= a and b;

end decoder2_4_arc;

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