Friday, 11 April 2014

Video Learning Series : Interfacing LED & Switch ::: Task - 3 with Codes & Video






 Video Learning Series : Interfacing LED & Switch ::: Task - 3




https://www.youtube.com/watch?v=P5hYdB_n6xo&list=UU91Msf7ixvSGlnx_RsKTd7Q
Click Here For Video ::: Video Learning Series (vhdlbynaresh.blogspot.com)



Video Link -
https://www.youtube.com/watch?v=P5hYdB_n6xo&list=UU91Msf7ixvSGlnx_RsKTd7Q


TASK 3  ::::    Interfacing LED & Switch With Cyclone II FPGA Device. -
Description -    LED's Starts Blinking when Switch is pressed & Remains same as it's last update when Switch is released.
In our video we take 8 LED's as output packed in 7- segment package.


VHDL Code -


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sl3 is
port (clk : in std_logic;
din : in std_logic;
dout : out std_logic_vector (7 downto 0));
end sl3;

architecture sl2_arc of sl3 is
begin
    p0 : process (clk,din) is
    variable m : std_logic_vector (24 downto 0) := (others=>'0');
    begin
        if (rising_edge (clk)) then
            m := m + 1;
        end if;
        if (din='0') then
            case m(24) is
                when '0' => dout <= "00000000";
                when others => dout <= "11111111";
            end case;
        end if;
    end process p0;
       
end sl2_arc;




Please revert with your suggestions, likes and comments to make this video series successful and helpful to others.

I would love to read your suggestions and comments here below

Best Regard //
Naresh Singh Dobal
nsdobal@gmail.com





Video Learning Series : Interfacing LED & Switch ::: Task - 2 with Codes & Video






 Video Learning Series : Interfacing LED & Switch ::: Task - 2


https://www.youtube.com/watch?v=rmpQ8F0dziY&list=UU91Msf7ixvSGlnx_RsKTd7Q   
Click Here For Video  ::: Video Learning Series (vhdlbynaresh.blogspot.com)



Video Link  -
https://www.youtube.com/watch?v=rmpQ8F0dziY&list=UU91Msf7ixvSGlnx_RsKTd7Q


 TASK 2  ::::    Interfacing LED & Switch With Cyclone II FPGA Device. -
Description -    LED's Starts Blinking when Switch is pressed & goes OFF when Switch is released.
In our video we take 8 LED's as output packed in 7- segment package.


VHDL Code -



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sl2 is
port (clk : in std_logic;
din : in std_logic;
dout : out std_logic_vector (7 downto 0));
end sl2;

architecture sl2_arc of sl2 is  --frequncy is 50 MHz
begin
    p0 : process (clk,din) is
    variable m : std_logic_vector (24 downto 0) := (others=>'0');
    begin
        if (rising_edge (clk)) then
            m := m + 1;
        end if;
        if (din='0') then
            case m(24) is
                when '0' => dout <= "00000000";
                when others => dout <= "11111111";
            end case;
        else
            dout <= (others => '0');
        end if;
    end process p0;
       
end sl2_arc;


 Please revert with your suggestions, likes and comments to make this video series successful and helpful to others.

I would love to read your suggestions and comments here below

Best Regard //
Naresh Singh Dobal
nsdobal@gmail.com

Video Learning Series : Interfacing LED & Switch ::: Task - 1 with Codes & Video






Video Learning Series : Interfacing LED & Switch  :::  Task - 1



https://www.youtube.com/watch?v=Ea_N3f_JQMc&list=UU91Msf7ixvSGlnx_RsKTd7Q
Click Here For Video ::: Video Learning Series (vhdlbynaresh.blogspot.com)


Video Link  - 
https://www.youtube.com/watch?v=Ea_N3f_JQMc&list=UU91Msf7ixvSGlnx_RsKTd7Q


 TASK 1  ::::    Interfacing LED & Switch With Cyclone II FPGA Device. - 
Description -    LED goes  ON when Logic 1 is given by switch as input & goes OFF when Logic '0' is given by switch as input.
In our video we take 8 LED's as output packed in 7- segment package.


VHDL Code -  

library ieee;
use ieee.std_logic_1164.all;

entity sl1 is
port (din : in std_logic ;
dout : out std_logic_vector (7 downto 0));
end sl1;

architecture sl1_arc of sl1 is
begin

dout <= "00000000" when din='0' else
"11111111";

end sl1_arc;



Please revert with your suggestions, likes and comments to make this video series successful and helpful to others.

I would love to read your suggestions and comments here below
Best Regard //
Naresh Singh Dobal
nsdobal@gmail.com

Tuesday, 19 November 2013

VHDL Lab Exercise ::: Exercise 8






VHDL Lab Exercise   :::   Exercise 8

LAB- 8  DESIGN OF SHIFT REGISTERS AND FLIP-FLOPS USING STRUCTURAL MODEL.



VHDL Lab Exercise 8 :: VHDL with Naresh Singh Dobal Learning Series.


If you feel any difficulties in any assignment then follow the below link...



I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com

VHDL Lab Exercise ::: Exercise 7





VHDL Lab Exercise   :::   Exercise 7


LAB5  COMBINATIONAL SYSTEM DESIGN USING STRUCTURAL MODEL.



VHDL Lab Exercise 7 :: VHDL with Naresh Singh Dobal Learning Series.




If you feel any difficulties in any assignment then follow the below link...



I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com

VHDL Lab Exercise ::: Exercise 6






VHDL Lab Exercise   :::   Exercise 6

LAB 6 : HARDWARE PERIPHERALS  & SYSTEM DESIGNS.


Lab Exercise 6 :: VHDL with Naresh Singh Dobal Learning Series.



If you feel any difficulties in any assignment then follow the below link...



I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com

VHDL Lab Exercise ::: Exercise 5





VHDL Lab Exercise   :::   Exercise 5

LAB5 : COUNTERS AND FREQUENCY DIVIDERS.


Lab Exercise 5 : VHDL with Naresh Singh Dobal Learning Series.


If you feel any difficulties in any assignment then follow the below link...



I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com

VHDL Lab Exercise ::: Exercise 4






VHDL Lab Exercise   :::   Exercise 4 -


LAB4 : LATCHES & FLIP-FLOPS & ALU.



Lab Exercise 4 : VHDL with Naresh Singh Dobal Learning Series.



If you feel any difficulties in any assignment then follow the below link...



I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com

VHDL Lab Excercise ::: Exercise 3






VHDL Lab Exercise   :::   Exercise 3 -

LAB 3 : COMBINATIONAL SYSTEM DESIGN USING BEHAVIOR MODELLING STYLE.


Lab Exercise 3 :  VHDL with Naresh Singh Dobal Learning Series.
Lab Exercise 3-b ::  VHDL with Naresh Singh Dobal Learning Series.


Task1 :      Write a VHDL code for Full adder using if-else.
Task2:       Write a VHDL code for Full subtractor using if-else.
Task3:       Write a VHDL code for 4:1 Multiplexer using if-else.
Task4:       Write a VHDL code for 1:4 Demultiplexer using if-else.
Task5:       Write a VHDL code for a 8:3 Encoder using if-else.
Task6:       Write a VHDL code for a 3:8 Decoder using if-else.
Task7:       Write a VHDL code for Full adder using case.
Task8 :      Write a VHDL code for Full subtractor using case.
Task9:       Write a VHDL code for 4:1 Multiplexer using case.
Task10:     Write a VHDL code for 1:4 Demultiplexer using case.
Task11:     Write a VHDL code for 8:3 Encoder using case.
Task12:     Write a VHDL code for 3:8 Decoder using case.
Task13:     Write a VHDL code for 3 bit comparator using if-else.
Task14:     Write a VHDL code for BINARY TO GRAY converter using if-else.
Task15:     Write a VHDL code for GRAY TO BINARY converter using case.


If you feel any difficulties in any assignment then follow the below link...



I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com

VHDL Lab Exercise ::: Exercise 2






VHDL Lab Exercise   :::   Exercise 2 -

LAB2 : COMBINATIONAL SYSTEM DESIGN USING DATA FLOW MODELLING STYLE.

Lab Exercise 2a :: VHDL with Naresh Singh Dobal Learning Series.
Lab Exercise 2-b :: VHDL with Naresh Singh Dobal Learning Series.




Task1 :      Write a VHDL code for all gates using with-select.
Task2:       Write a VHDL code for Full adder using with-select.
Task3:       Write a VHDL code for Full subtractor using with-select. .
Task4:       Write a VHDL code for 4:1 Multiplexer using With-select.
Task5:       Write a VHDL code for a 1:4 Demultiplexer using with-select.
Task6:       Write a VHDL code for a 8:3 Encoder using With-Select.
Task7:       Write a VHDL code for a 3:8 Decoder using With-Select.
Task8 :      Write a VHDL code for all gates using when-else.
Task9:       Write a VHDL code for Full adder using when-else.
Task10:     Write a VHDL code for Full subtractor using when-else.
Task11:     Write a VHDL code for 4:1 Multiplexer using When-else. .
Task12:     Write a VHDL code for a 1:4 Demultiplexer using when-else.
Task13:     Write a VHDL code for a 8:3 Encoder using When-else.
Task14:     Write a VHDL code for a 3:8 Decoder using When-else.
Task15:     Write a VHDL code for 8:3 Encoder with Priority using when-else.
Task16:     Write a VHDL code for BINARY to GRAY Converter using with-select.
Task17:     Write a VHDL code for GRAY to BINARY Converter using with-select.
Task18:     Write a VHDL code for BINARY to GRAY Converter using when-else.
Task19:     Write a VHDL code for GRAY to BINARY Converter using when-else.
Task20:     Write a VHDL code for BINARY to EXCESS-3 using With-select.
Task21:     Write a VHDL code for BINARY TO GRAY Converter using equation.
Task22:     Write a VHDL code for GRAY to BINARY Converter using equations.
Task23:    Write a VHDL code for BINARY TO EXCESS-3 using equations.



If you feel any difficulties in any assignment then follow the below link...



I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact us at nsdobal@gmail.com

VHDL Lab Exercise :: Exercise 1






VHDL Lab Exercise   :::   Exercise 1 -


LAB 1:  COMBINATIONAL SYSTEM DESIGN USING BASIC GATES AND EQUATIONS.
VHDL Lab Exercise 1 :: VHDL with Naresh Singh Dobal Learning Series.




Task1 :   Write a VHDL Program for all Logic Gates.
Task2 :   Write a VHDL code for a Half Adder using Digital Electronics.
Task3 :   Write a VHDL code for a Full Adder using Digital Electronics.
Task4 :   Write a VHDL code for a Half Subtractor using Digital Electronics.
Task5 :   Write a VHDL code for a Full Subtractor using Digital Electronics.
Task6:    Write a VHDL code for a 4:1 Multiplexer using Digital Electronics.
Task7:    Write a VHDL code for a 1:4 Multiplexer using Digital Electronics.
Task8:    Write a VHDL code for a 4:2 Encoder using Digital Electronics.
Task9:    Write a VHDL code for a 2:4 Decoder using Digital Electronics.
Task10:  Write a VHDL code for 1 bit Comparator using Digital Electronics. 


If you feel any difficulties in any assignment then follow the below link...



I would love to read your suggestions and comments here below.
My name is Naresh Singh Dobal, for any query contact me at nsdobal@gmail.com

Tuesday, 12 November 2013

A Small Discussion about VHDL & Verilog HDL...






A Small Discussion about VHDL & Verilog HDL -


VHDL or Verilog HDL - A small discussion (VHDL with Naresh Singh Dobal learning Series).



Verilog HDL is easier to understand and use, It is very effectively used for simulation and synthesis. but it lacks for system level or complex designing. It is promoted by OVI (Open Verilog International). It is widely used for ASIC designing or lower level design (RTL or  lower), but this results in faster simulation and effective synthesis. Mostly used in North America, Asia & Japan, but not popular in Europe.

As comparable to verilog HDL, VHDL is more complex, thus difficult to learn and use. But this offers more flexibility of designing. Since VHDL is better suited for handling very complex systems, so it is now gaining popularity. VHDL  is mainly promoted by VHDL international. VHDL is relatively weaker in lower designs. But superior in system level design. Many believes that in long terms presents better condition and adaptability than its competitors. This language is widely used in Europe, significantly used in US and Canada, but this disliked in Japan...


Both the HDL's are used to describe electronic systems.
The function of systems is to get input data from it's environment and give output some data in return.
In verilog HDL this is called a module which is a basic building block in Verilog HDL, and in VHDL this is defined in Entity & Architecture Pair.
 Both the Languages are IEEE Standard.


I would love to read your suggestions and comments here below,
Best Regard //
Naresh Singh Dobal
nsdobal@gmail.com

Monday, 11 November 2013

Basics of VHDL Language Execution process concurrent and sequential







Basics of VHDL Execution Process (Concurrent and Sequential) -


Basics of VHDL Language Execution process  (VHDL with Naresh Singh Dobal learning series). 



Hello Friends,
       Before start writing of codes in VHDL for digital systems you must know about the execution of VHDL language, you should know that how the tools process the VHDL code. This is a very important concept you should understand for proficiency in VHDL.

VHDL can be programmed in following execution pattern.
1.Concurrent Execution.
2.Sequential Execution.
 
 
VHDL can work on –
1.Concurrent Language.
2.Sequential Language.
3.Net-List Language.
4.Timing Specification.
5.Waveform Generation Language.
 
 
Before describing all above language I want to ask a question to you…….This will help you to understand the concept.
My question is, -  Suppose we have a real life IC and we are using that in a hardware circuit and we have four inputs and four outputs in IC, so is it possible to give inputs one by one I mean is it possible to give it input to first pin and others are idle or after some time input switch to second pin. And so on…………………. Is it ??????????
Answer is No, Obviously this is not possible in real life, If one IC having four inputs and then we have to give all the inputs in same time, doesn’t matter our inputs are affecting the outputs or not. But we have to give all the inputs to all pins at a same time.

That means we can easily say that all the real life IC working on concurrent fashion. And all our HDL tools are also performs concurrent execution to get real life working environment. And we have to define all the connections of gates and Registers threw nets, or we must define the flow of data from input to output. But in that manner we must know the structure of hardware system. This is a very difficult task for designers for complex system. As we know today we have multi-billion transistors in a single IC chip, so this is practically impossible to design a complete system in term of structure.  


Next is Sequential Execution -
I am going to start describing this with the most widely used execution process which is used in multiple languages. If we talk about software languages most of them are worked on Sequential processing or line by line processing concept. VHDL or Verilog HDL both are working on Sequential language as well. This makes our designing process very easy, because using of different sequential concepts like if-else, case, loops, edge-triggering etc. so now if we have to design a 4 bit comparator we just write     

If (a=b) then
    eq <= ‘1’;
Else
   eq <= ‘0’;
End if;


** where a and b are 4 bit inputs and eq is 1 bit output.
But my question to you is, how you define a sequential language with a hardware part. Because in sequential execution statements will perform according to line by line, and in hardware all process should be taken at same time. So how we configure our system (designed using sequential execution) in real life hardware……..???????
Let me explain –
Firt you should know what is configured in our hardware, We code our system in HDL (concurrent + sequential) but that hdl code never configured with hardware, what is configured – RTL, that means we have to convert our HDL code into RTL structure before configuring. Which provide physical connection of all physical registers. Registers which I have defined in my previous post (individual basic gate or a combination of gates).
Now I believe that you understand both the executions i.e, concurrent or sequential.

** Also remember normally all our HDL's perform concurrent execution, If some one ask you that VHDL is basically what type of language then answer is -
VHDL is Concurrent type of language, but it supports Sequential language as well.
and If we need sequential language anywhere then we convert our execution from concurrent to sequential, later I will tell you how we convert the way of execution and what keywords designers use for that purpose.


Net list language –
Net list language is also working on Concurrent execution. But only the difference is in net list language we design our system by defining the basic elements like gates or collection of gates (called modules and registers). 

** Above three languages are used for designing purpose.


Other two languages i.e. Timing specification and  waveform generation language are used for verification purpose. In brief-
Timing Specification -  we can define the flow of data from input to output in our simulation screen but again this can not be implement in real life hardware because you can't specify the time of flow of data. So timing specification language only use in writing of test benches. Same a waveform generation language,
Is used for creation of waveforms, basically this is a  algorithm to get the same output by minimizing the processing time.


For more information you can go with our video tutorial series.
I would love to read your comments and suggestions in comment bar below…
My name is “Naresh Singh Dobal”, for any query you can write us directly at     nsdobal@gmail.com

 
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